As technology scaling enters into nanometer geometries, there is a significant increase in performance uncertainty of System-on-chip designs due to parametric variations. Process variability is posing an increasing challenge in timing analysis for designers. The traditional corner-based approach is not effective anymore and it will induce pessimism. Therefore, statistical timing analysis has become very important in overcoming the weakness of the traditional methods. By constructing statistical timing models for variations, chip performance and parametric yield will be more accurately predicted. In this work, variability aware statistical timing models of standard cells and system level interconnects are developed by using SPICE simulations, and statistical timing analysis flow and characterization automation are summarized.